1. Technical Field
The present invention relates generally to the field of integrated circuit design, and, more specifically, to the field of logic synthesis of electronic circuit designs. Yet more specifically, the present invention relates to a method, system, and computer program product for correcting anticipated problems related to global routing during logic synthesis.
2. Description of Related Art
Microelectronic integrated circuits consist of a large number of electronic components that are fabricated by layering several different materials on a silicon base or wafer. The design of an integrated circuit transforms a circuit description into a geometric description which is known as a layout. The process of converting the functional specifications of an electronic circuit into a layout is called the physical design.
The objective of physical design is to determine an optimal arrangement of devices in a plane or in a three dimensional space, and an efficient interconnection or routing scheme between the devices to obtain the desired functionality.
An integrated circuit chip (hereafter referred to as an xe2x80x9cICxe2x80x9d or a xe2x80x9cchipxe2x80x9d) comprises cells and connections between the cells formed on a surface of a semiconductor substrate. The IC may include a large number of cells and require complex connections between the cells.
A cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements grouped to perform a function. Each of the cells of an IC may have one or more pins, each of which, in turn, may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip.
A net is a set of two or more pins which must be connected. Because a typical chip has thousands, tens of thousands, or hundreds of thousands of pins which must be connected in various combinations, the chip also includes definitions of thousands, tens of thousands, or hundreds of thousands of nets, or sets of pins. All the pins of a net must be connected. The number of the nets for a chip is typically in the same order as the order of the number of cells on that chip. Commonly, a majority of the nets include only two pins to be connected; however, many nets comprise three or more pins.
The input to the physical design problem is a circuit diagram, and the output is the layout of the circuit. This is accomplished in several stages including partitioning, floor planning, placement, routing and compaction.
The objective of the routing phase is to complete the interconnections between cells according to the specified netlist. First, the space not occupied by cells, which is called the routing space, is partitioned into rectangular regions called channels. The goal of a router is to complete all circuit connections using the shortest possible wire length and using only the channel.
Routing is usually done in two phases referred to as the global routing and detailed routing phases. In global routing, connections are completed between the cells of the circuit disregarding the exact geometric details of each wire and terminal. For each wire, a global router finds a list of channels that are to be used as a passageway for that wire. In other words, global routing specifies the loose route of a wire through different regions of the routing space.
Global routing is followed by detailed routing which completes point-to-point connections between terminals on the blocks. Loose routing is converted into exact routing by specifying the geometric information such as width of wires and their layer assignments. Detailed routing includes the exact channel routing of wires.
Due to the large number of components and the exacting details required by the fabrication process, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use Computer Aided Design (CAD) tools.
During logic synthesis, a high-level electronic circuit design is converted into a list of books and their interconnections, called the xe2x80x9cnetlist.xe2x80x9d A xe2x80x9cbookxe2x80x9d refers herein to an identifiable primitive function (i.e., xe2x80x9ccellxe2x80x9d). This includes a pre-designed circuit for performing a certain Boolean function, together with certain information about the circuit. During the synthesis process, a strength for each book is selected. Assumptions are made during the selection of the strength of each book about the global routing of the wiring of the circuit. For example, it is assumed that the wire will be reasonable in length. However, the actual wire after routing may be xe2x80x9cscenicxe2x80x9d in that it does not go straight between the output pin of one book and the input pin of the load book. When this occurs, some books that are the source of the wire may have problems because they may now be too small to drive the actual load represented by the actual wire. Correcting this after the fact causes an xe2x80x9cextraxe2x80x9d iteration though the physical design process, resulting in extra time to market and reduced profit.
Therefore, a need exists for a method, system, and product for correcting anticipated problems related to global routing during logic synthesis.
A method, system, and computer product are disclosed for correcting anticipated problems related to global routing during logic synthesis. Synthesis is begun of a circuit design that includes multiple logic functions. During the synthesis, multiple logic books are selected to use to implement the logic function. Also during synthesis, at least one of the logic books is identified that is sensitive to a change in output wire capacitance of the identified logic book, where a value of the output wire capacitance is related to a routing of the wire. A strength of each identified logic book is then increased.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.